DDR2 667MHz, 533MHz, 800MHz
240-pin socket type dual in line memory module
Lead-free 1.8V power supply
Data rate: 667Mbps/533Mbps/800Mbps
1.8V (SSTL-18 compatible) I/O
Double-data-rate architecture: Two data transfers per clock cycle
Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with
Data, to be used in capturing data at the receiver
DQS is edge aligned with data for reading: Center aligned with data for writing
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge: Data and data mask referenced to both
Edges of DQS
Four internal banks for concurrent operation (component)
Data mask (DM) for write data
Burst lengths: 4, 8
CAS latency (CL): 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
7.8us average periodic refresh interval
Posted CAS by programmable additive latency for better command and data bus efficiency
Off-chip-driver impedance adjustment and on-die-termination for better signal quality
DQS can be disabled for single-ended data strobe operation